The present invention relates to integrated circuits with MOS (Metal Oxide Semiconductor) transistors having a single type of charge carriers and, more particularly, to an output interface circuit for a three-state logic circuit of such an integrated circuit.
In the following sections a description will be given of circuits that use only N-channel MOS transistors in which the charge carriers are electrons. It will be understood, however, that the same description is also applicable to similar circuits using only P-channel MOS transistors in which the charge carriers are holes, provided that the polarities of the voltages are reversed.
As a rule, the three logic states transmitted from the interface circuit to an output terminal of the integrated circuit are defined by the voltage values that can be assumed by the output terminal. More specifically, a first state is characterized by a high-voltage level, i.e., a voltage which is close to the voltage of the positive terminal of the power supply; a second state is characterized by a low-voltage level, i.e., a voltage which is close to the voltage of the negative terminal of the power supply; and the third state is defined by an intermediate level determined by the user circuit connected to the output. From the viewpoint of the current supplied to the user circuit, i.e., of the impedance offered by the output of the interface circuit, the first state offers a high impedance relative to the negative terminal of the power supply and a low impedance relative to the positive terminal of the power supply, the second state offers a low impedance relative to the negative pole and a high impedance relative to the positive pole, and the third state offers a high impedance relative to both terminals of the power supply. In many applications, particularly in those utilizing a relatively low supply voltage, e.g., 5 volts, it is important that in the state characterized by the high-voltage output level, the voltage at the output terminal must be very close to the voltage of the positive terminal of the power supply. This requirement can be easily complied with by using an additional power supply capable of supplying a higher voltage than the main power supply voltage. However, when it is not possible or desired to use such an additional power supply, or if only a high-voltage generator is available with a very high internal impedance and which, therefore, is unable to supply the necessary power, one usually resorts to circuit arrangements which, by means of one or more capacitors, make it possible during limited period of time to reach higher voltages than the power supply voltage. The latter solution, however, is not convenient in applications where the dwell time of the output signal may be relatively long, because this requires the use of high-capacity capacitors which, therefore, cannot be integrated, or can only be integrated with a great outlay of the useful area of the integrated circuit.